1. Technical Field
The present invention relates in general to a data processing system, and in particular to a method and system for performance monitoring within a data processing system. Still more particularly, the present invention relates to a method and system for counting events within a data processing system in which a plurality of counters may be selectively linked.
2. Description of the Related Art
Within state-of-the-art processors, facilities are often provided which enable the processor to count occurrences of software-selectable events and to time the execution of processes within an associated data processing system. These facilities are known as the performance monitor of the processor.
Events within the data processing system are counted by one or more counters within the performance monitor. The operation of such counters is managed by a control register, which is comprised of a plurality of bit fields. In general, both the control register and the counters are readable and writable by software. Thus, by writing values to the control register, a user may select the events within the data processing system to be monitored and specify the conditions under which the counters are enabled.
The performance monitor has many applications which enable a user to optimize the performance of a data processing system. For example, software engineers may utilize timing data from the performance monitor to optimize programs by relocating branch instructions and memory accesses. In addition, the performance monitor may be utilized to gather data about the access times to the data processing system's L1 cache, L2 cache, and main memory. Utilizing this data, system designers may identify performance bottlenecks specific to particular software or hardware environments.
Because the number of occurrences of an event, such as a memory access, may be large, state-of-the-art performance monitors typically utilize large counters (e.g., 32-bit counters). In addition, because each counter counts occurrences of only a single event, state-of-the art performance monitors utilize a number of counters to provide a broad description of system performance. Consequently, to provide the functionality of multiple large counters, the processor chip area allocated to the performance monitor becomes large as the size and number of counters increases. Because the cost of processor fabrication rises concomitantly with a processor's die size, the additional functionality provided by additional counters and increased counter size is often sacrificed due to economic considerations.
Consequently, it would be desirable to provide a method and system for counting events within a data processing system which reduce the size of a plurality of counters within a performance monitor without reducing the maximum number of event occurrences which may be counted without overflow.